Design of the low-voltage CMOS analog multiplier

Analog Multiplier is an electronic device that performs linear multiplication of two continual input signals. It found its extensive uses in analog signal processing. In this report, different architectures of multipliers reported are discussed. Advantages and disadvantages of each topology were stu...

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Main Author: Chong, Hauo Wah.
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: 2010
Subjects:
Online Access:http://hdl.handle.net/10356/40789
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-407892023-07-07T17:08:18Z Design of the low-voltage CMOS analog multiplier Chong, Hauo Wah. Siek Liter School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering Analog Multiplier is an electronic device that performs linear multiplication of two continual input signals. It found its extensive uses in analog signal processing. In this report, different architectures of multipliers reported are discussed. Advantages and disadvantages of each topology were studied before the final design was proposed. The multiplier proposed is operating in saturation region, which follows the concept of Type V multiplier discussed in literature review. The structure of this final design is made up with four different parts: single-ended to differential conversion, impedance conversion, trans-conductance multiplier and lastly the modified cascade current mirror to deliver the output signal. These different parts of the circuit serve to improve the performances of the multiplier. Design of current sources and output buffer are described in this report as well. 0.18um process technology was adopted. Simulation in software cadence was conducted to verify the performance of the proposed structure. The proposed structure is operational with 1.3 V supply voltage and maximum ±0.2 V input signals. THD performance is less than 5% at 100MHz. It can drive an output load of at least 10kΩ in parallel with 150pF. Operating temperature is between -45oC and 85oC, typically at room temperature, which is 27oC. Bachelor of Engineering 2010-06-22T01:41:13Z 2010-06-22T01:41:13Z 2010 2010 Final Year Project (FYP) http://hdl.handle.net/10356/40789 en Nanyang Technological University 97 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering
spellingShingle DRNTU::Engineering
Chong, Hauo Wah.
Design of the low-voltage CMOS analog multiplier
description Analog Multiplier is an electronic device that performs linear multiplication of two continual input signals. It found its extensive uses in analog signal processing. In this report, different architectures of multipliers reported are discussed. Advantages and disadvantages of each topology were studied before the final design was proposed. The multiplier proposed is operating in saturation region, which follows the concept of Type V multiplier discussed in literature review. The structure of this final design is made up with four different parts: single-ended to differential conversion, impedance conversion, trans-conductance multiplier and lastly the modified cascade current mirror to deliver the output signal. These different parts of the circuit serve to improve the performances of the multiplier. Design of current sources and output buffer are described in this report as well. 0.18um process technology was adopted. Simulation in software cadence was conducted to verify the performance of the proposed structure. The proposed structure is operational with 1.3 V supply voltage and maximum ±0.2 V input signals. THD performance is less than 5% at 100MHz. It can drive an output load of at least 10kΩ in parallel with 150pF. Operating temperature is between -45oC and 85oC, typically at room temperature, which is 27oC.
author2 Siek Liter
author_facet Siek Liter
Chong, Hauo Wah.
format Final Year Project
author Chong, Hauo Wah.
author_sort Chong, Hauo Wah.
title Design of the low-voltage CMOS analog multiplier
title_short Design of the low-voltage CMOS analog multiplier
title_full Design of the low-voltage CMOS analog multiplier
title_fullStr Design of the low-voltage CMOS analog multiplier
title_full_unstemmed Design of the low-voltage CMOS analog multiplier
title_sort design of the low-voltage cmos analog multiplier
publishDate 2010
url http://hdl.handle.net/10356/40789
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