Design and implementation of formal verification tool for combinational circuits using automatic test pattern generation

• 主要作者: Tan, Sue Yee.
• 其他作者: Gwee Bah Hwee
• 格式: Final Year Project
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: http://hdl.handle.net/10356/40907
• 機構: Nanyang Technological University

Functional Verification or Logical Simulation is an important phase in Digital Design Flow. It is to ensure that the functionality of the design remains the same as the initial desired functionality at any point of time in the whole process, before advancing to the next level. If errors are detected...