Design of high performance, low power latches and flip-flops
With the advent of hand-held computing devices that require functionality rivaling the desktop, Low Power, High Performance systems have become the norm rather than the exception. The clocking network with its 20-40% contribution to the overall power dissipation is becoming a major obstacle in imp...
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| 主要作者: | |
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2011
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/42657 |
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| 總結: | With the advent of hand-held computing devices that require functionality
rivaling the desktop, Low Power, High Performance systems have become the
norm rather than the exception. The clocking network with its 20-40% contribution to the overall power dissipation is becoming a major obstacle in implementing these systems. Hence the need for high performance basic sequential elements with low power dissipation is steadily growing. The aim of
this project is to develop latches and flip-flops to fulfill this need.
Since latches and flip-flops are used to store logic values, the traditional
measures of area, speed and power dissipation are not sufficient to access their quality. In this project, a set of quality measures has been developed for these
basic sequential elements. |
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