Design of high performance, low power latches and flip-flops
With the advent of hand-held computing devices that require functionality rivaling the desktop, Low Power, High Performance systems have become the norm rather than the exception. The clocking network with its 20-40% contribution to the overall power dissipation is becoming a major obstacle in imp...
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| التنسيق: | Theses and Dissertations |
| اللغة: | English |
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2011
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| الوصول للمادة أونلاين: | http://hdl.handle.net/10356/42657 |
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sg-ntu-dr.10356-426572020-09-27T20:17:49Z Design of high performance, low power latches and flip-flops Shridhar Mubaraq Mishra. Yeo Kiat Seng School of Applied Science DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits With the advent of hand-held computing devices that require functionality rivaling the desktop, Low Power, High Performance systems have become the norm rather than the exception. The clocking network with its 20-40% contribution to the overall power dissipation is becoming a major obstacle in implementing these systems. Hence the need for high performance basic sequential elements with low power dissipation is steadily growing. The aim of this project is to develop latches and flip-flops to fulfill this need. Since latches and flip-flops are used to store logic values, the traditional measures of area, speed and power dissipation are not sufficient to access their quality. In this project, a set of quality measures has been developed for these basic sequential elements. Master of Philosophy (Computer Engineering) 2011-01-06T04:00:06Z 2011-01-06T04:00:06Z 1999 1999 Thesis http://hdl.handle.net/10356/42657 en 177 p. application/pdf |
| institution |
Nanyang Technological University |
| building |
NTU Library |
| country |
Singapore |
| collection |
DR-NTU |
| language |
English |
| topic |
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| spellingShingle |
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Shridhar Mubaraq Mishra. Design of high performance, low power latches and flip-flops |
| description |
With the advent of hand-held computing devices that require functionality
rivaling the desktop, Low Power, High Performance systems have become the
norm rather than the exception. The clocking network with its 20-40% contribution to the overall power dissipation is becoming a major obstacle in implementing these systems. Hence the need for high performance basic sequential elements with low power dissipation is steadily growing. The aim of
this project is to develop latches and flip-flops to fulfill this need.
Since latches and flip-flops are used to store logic values, the traditional
measures of area, speed and power dissipation are not sufficient to access their quality. In this project, a set of quality measures has been developed for these
basic sequential elements. |
| author2 |
Yeo Kiat Seng |
| author_facet |
Yeo Kiat Seng Shridhar Mubaraq Mishra. |
| format |
Theses and Dissertations |
| author |
Shridhar Mubaraq Mishra. |
| author_sort |
Shridhar Mubaraq Mishra. |
| title |
Design of high performance, low power latches and flip-flops |
| title_short |
Design of high performance, low power latches and flip-flops |
| title_full |
Design of high performance, low power latches and flip-flops |
| title_fullStr |
Design of high performance, low power latches and flip-flops |
| title_full_unstemmed |
Design of high performance, low power latches and flip-flops |
| title_sort |
design of high performance, low power latches and flip-flops |
| publishDate |
2011 |
| url |
http://hdl.handle.net/10356/42657 |
| _version_ |
1681058688885850112 |