VLSI implementation of a parser for MPEG-2 systems program stream

This report presents the VLSI design and implementation of a Parser for Program Stream of MPEG2 System Layer. The MPEG2 Program Stream Syntax, the Parser architecture, HDL implementation, simulation, synthesis and design timing analysis are discussed in detail.

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Bibliographic Details
Main Author:	Ashwin Pai Ballambettu.
Other Authors:	Ho, Duan Juat
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic systems DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Online Access:	http://hdl.handle.net/10356/4279
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4279
record_format	dspace
spelling	sg-ntu-dr.10356-42792023-07-04T15:15:27Z VLSI implementation of a parser for MPEG-2 systems program stream Ashwin Pai Ballambettu. Ho, Duan Juat School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems This report presents the VLSI design and implementation of a Parser for Program Stream of MPEG2 System Layer. The MPEG2 Program Stream Syntax, the Parser architecture, HDL implementation, simulation, synthesis and design timing analysis are discussed in detail. Master of Science (Consumer Electronics) 2008-09-17T09:48:13Z 2008-09-17T09:48:13Z 2005 2005 Thesis http://hdl.handle.net/10356/4279 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Electronic systems DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Electronic systems DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Ashwin Pai Ballambettu. VLSI implementation of a parser for MPEG-2 systems program stream
description	This report presents the VLSI design and implementation of a Parser for Program Stream of MPEG2 System Layer. The MPEG2 Program Stream Syntax, the Parser architecture, HDL implementation, simulation, synthesis and design timing analysis are discussed in detail.
author2	Ho, Duan Juat
author_facet	Ho, Duan Juat Ashwin Pai Ballambettu.
format	Theses and Dissertations
author	Ashwin Pai Ballambettu.
author_sort	Ashwin Pai Ballambettu.
title	VLSI implementation of a parser for MPEG-2 systems program stream
title_short	VLSI implementation of a parser for MPEG-2 systems program stream
title_full	VLSI implementation of a parser for MPEG-2 systems program stream
title_fullStr	VLSI implementation of a parser for MPEG-2 systems program stream
title_full_unstemmed	VLSI implementation of a parser for MPEG-2 systems program stream
title_sort	vlsi implementation of a parser for mpeg-2 systems program stream
publishDate	2008
url	http://hdl.handle.net/10356/4279
_version_	1772827195695169536

VLSI implementation of a parser for MPEG-2 systems program stream

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