Hazard simulation of asynchronous logic circuits

• Main Author: Gong, Jie.
• Other Authors: Wong, Eddie Moon Chung
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/4304
• Institution: Nanyang Technological University

Asynchronous circuits have recently played an increasing role in the design of high speed VLSI system, since they can achieve higher performance with lower power consumption. Also, the development of several new asynchronous design methodologies has made the design of much larger and more complex circuits possible. However, asynchronous circuits are sensitive to hazards, which may cause improper circuit operation and should be avoided in the design stage. Although almost all design styles adopt some techniques to eliminate hazards, the design implementation operates correctly only when the time relationship specified in the corresponding design style is satisfied. Furthermore, during the process of mapping a logic-level description of the resultant design that is hazard-free for transitions of interest into a technology-specific implementation composed of an interconnection of elements from semi-custom cell library, new hazards may be introduced again. Thus, verification of the implementation of asynchronous circuits is quite necessary.