Sub-threshold SRAM cell design for ultra low-power applications
With the continuous development of the technology nowadays, the application of domains of memory components such as Static Random Access Memory (SRAM) have become increasingly broader, so are the demands for the SRAM. In many situations, the power consumption has been the design aspect that is of ut...
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2011
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/45006 |
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| 總結: | With the continuous development of the technology nowadays, the application of domains of memory components such as Static Random Access Memory (SRAM) have become increasingly broader, so are the demands for the SRAM. In many situations, the power consumption has been the design aspect that is of utmost necessity and concern by the consumers. Under this circumstance, one potential solution is to efficiently design the SRAM memory cell so that it is able to operate in the sub-threshold region, which could significantly decrease the power consumption. Although there are many SRAM memory cells designed for the sub-threshlod region and they have very good performance with the previous CMOS technology, in terms of 65 nm technology today the performance of these SRAM memory cells is totally different with the developments of CMOS technology and scale down of CMOS channel width. In this final year project, two novelly designed memory cells are proposed for better performance in the sub-threshold region based on a 65 nm technology from United Microelectronics Corporation (UMC). Their performance is compared with the existing memory cells to evaluate that they can operate very well in the sub-threshold region and they can efficiently decrease the power consumption without the increase of delay. |
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