Design of a low-voltage CMOS analogue multiplier

• المؤلف الرئيسي: Leow, Hee Boon.
• مؤلفون آخرون: Siek, Liter
• التنسيق: Theses and Dissertations
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/4598
• المؤسسة: Nanyang Technological University

The objective of this project is to design a low-voltage analogue multiplier operating on a 1.3V voltage supply and its' 3-dB bandwidth is expected to be about 100 KHz. This multiplier should be able to operate with the input signals of the 1.2V voltage swing and expect an output voltage swing...