Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms
84 p.
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| مؤلفون آخرون: | |
| التنسيق: | Theses and Dissertations |
| منشور في: |
2011
|
| الموضوعات: | |
| الوصول للمادة أونلاين: | http://hdl.handle.net/10356/46820 |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|
| المؤسسة: | Nanyang Technological University |
| id |
sg-ntu-dr.10356-46820 |
|---|---|
| record_format |
dspace |
| spelling |
sg-ntu-dr.10356-468202023-07-04T15:31:25Z Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms Vedavally Jayaraman Yu Yajun School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering 84 p. Improvements in VLSI technology have enabled digital filters to be used in an increasing number of application domains. In a full custom hardware implementation, the coefficient multiplier is the most expensive and the most important speed determining component. Consequently the primary concern in the design of filters for hardware implementation is to reduce the multiplier complexity. Many methods have been proposed to reduce the hardware complexity of digital filters. One of these methods is to approximate each coefficient value by a small number of signed power-of-two terms (SPT) as the number of SPT terms is proportional to the hardware complexity which is the aim of this thesis. Master of Science (Integrated Circuit Design) 2011-12-23T09:58:19Z 2011-12-23T09:58:19Z 2009 2009 Thesis http://hdl.handle.net/10356/46820 Nanyang Technological University application/pdf |
| institution |
Nanyang Technological University |
| building |
NTU Library |
| continent |
Asia |
| country |
Singapore Singapore |
| content_provider |
NTU Library |
| collection |
DR-NTU |
| topic |
DRNTU::Engineering::Electrical and electronic engineering |
| spellingShingle |
DRNTU::Engineering::Electrical and electronic engineering Vedavally Jayaraman Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms |
| description |
84 p. |
| author2 |
Yu Yajun |
| author_facet |
Yu Yajun Vedavally Jayaraman |
| format |
Theses and Dissertations |
| author |
Vedavally Jayaraman |
| author_sort |
Vedavally Jayaraman |
| title |
Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms |
| title_short |
Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms |
| title_full |
Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms |
| title_fullStr |
Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms |
| title_full_unstemmed |
Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms |
| title_sort |
algorithm and circuit design for conversion of binary numbers to signed power-of-two terms |
| publishDate |
2011 |
| url |
http://hdl.handle.net/10356/46820 |
| _version_ |
1772825697189888000 |