Low jitter frequency multiplier
182 p.
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Theses and Dissertations |
| Published: |
2011
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/46842 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| id |
sg-ntu-dr.10356-46842 |
|---|---|
| record_format |
dspace |
| spelling |
sg-ntu-dr.10356-468422023-07-04T16:16:35Z Low jitter frequency multiplier Yin, Jee Khoi Chan Pak Kwong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering 182 p. This thesis I explore the research in the area of low jitter frequency multipliers before proposing a novel new design for such a multiplier. The thesis begins with an analysis of the random and deterministic noise arising from conventional phaselocked loop (PLL) and delay-locked loop (DLL) based frequency multipliers. Although the DLL is a better candidate for use as a low jitter frequency multiplier, analysis shows that the jitter performance of the DLL can be jeopardized by the cascading structure of the delay cells. Thus, a new architectural form is proposed. In this design, the delay chain of the conventional DLL is replaced by a polyphase filter (PPF) to generate clock edges for frequency multiplication purposes. A fundamental jitter analysis shows that the random jitter performance of the proposed PPF frequency multiplier outperforms that of the conventional DLL. Because the clock edges generated by the PPF have a larger mismatch when compared to their DLL counterparts, an analog-based phase error calibration (PEC) circuit is proposed to reduce the phase error. In doing so, both the random and deterministic jitter can be minimized and a frequency multiplier with better jitter performance is achieved. DOCTOR OF PHILOSOPHY (EEE) 2011-12-23T10:00:16Z 2011-12-23T10:00:16Z 2010 2010 Thesis Yin, J. K. (2010). Low jitter frequency multiplier. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/46842 10.32657/10356/46842 Nanyang Technological University application/pdf |
| institution |
Nanyang Technological University |
| building |
NTU Library |
| continent |
Asia |
| country |
Singapore Singapore |
| content_provider |
NTU Library |
| collection |
DR-NTU |
| topic |
DRNTU::Engineering::Electrical and electronic engineering |
| spellingShingle |
DRNTU::Engineering::Electrical and electronic engineering Yin, Jee Khoi Low jitter frequency multiplier |
| description |
182 p. |
| author2 |
Chan Pak Kwong |
| author_facet |
Chan Pak Kwong Yin, Jee Khoi |
| format |
Theses and Dissertations |
| author |
Yin, Jee Khoi |
| author_sort |
Yin, Jee Khoi |
| title |
Low jitter frequency multiplier |
| title_short |
Low jitter frequency multiplier |
| title_full |
Low jitter frequency multiplier |
| title_fullStr |
Low jitter frequency multiplier |
| title_full_unstemmed |
Low jitter frequency multiplier |
| title_sort |
low jitter frequency multiplier |
| publishDate |
2011 |
| url |
https://hdl.handle.net/10356/46842 |
| _version_ |
1772828025853837312 |