A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration

• Main Authors: Yin, J. K., Chan, Pak Kwong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/92971; http://hdl.handle.net/10220/6253
• Institution: Nanyang Technological University

A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13- m CMOS process....