A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13- m CMOS process....
Saved in:
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2010
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/92971 http://hdl.handle.net/10220/6253 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Language: | English |