A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration

A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13- m CMOS process....

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Main Authors:	Yin, J. K., Chan, Pak Kwong
Other Authors:	School of Electrical and Electronic Engineering
Format:	Article
Language:	English
Published:	2010
Subjects:	DRNTU::Engineering::Electrical and electronic engineering
Online Access:	https://hdl.handle.net/10356/92971 http://hdl.handle.net/10220/6253
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Institution:	Nanyang Technological University
Language:	English

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spelling	sg-ntu-dr.10356-929712020-03-07T13:57:22Z A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration Yin, J. K. Chan, Pak Kwong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13- m CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and 9.33 ps (pk–pk) at 200-MHz output frequency, while achievable maximum static phase error of the calibration circuit is 2.4 ps. The calibration leads to the normalized rms jitter of 0.049%. Published version 2010-05-05T02:56:43Z 2019-12-06T18:31:44Z 2010-05-05T02:56:43Z 2019-12-06T18:31:44Z 2008 2008 Journal Article Yin, J. K., & Chan, P. K. (2008). A Low-Jitter Polyphase Filter Based Frequency Multiplier with Phase Error Calibration. IEEE Transactions on Circuits and Systems - II. 55(7), 663-667. 1549-7747 https://hdl.handle.net/10356/92971 http://hdl.handle.net/10220/6253 10.1109/TCSII.2008.921571 en IEEE transactions on circuits and systems - II © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 5 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering Yin, J. K. Chan, Pak Kwong A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
description	A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13- m CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and 9.33 ps (pk–pk) at 200-MHz output frequency, while achievable maximum static phase error of the calibration circuit is 2.4 ps. The calibration leads to the normalized rms jitter of 0.049%.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Yin, J. K. Chan, Pak Kwong
format	Article
author	Yin, J. K. Chan, Pak Kwong
author_sort	Yin, J. K.
title	A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
title_short	A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
title_full	A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
title_fullStr	A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
title_full_unstemmed	A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
title_sort	low-jitter polyphase-filter-based frequency multiplier with phase error calibration
publishDate	2010
url	https://hdl.handle.net/10356/92971 http://hdl.handle.net/10220/6253
_version_	1681038295662854144

A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration

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