Design of a low-power asynchronous multiplier
This thesis pertains to design and analysis of a 16-bit low-voltage (1.1 V) low-power asynchronous parallel multiplier targeted for a low-power asynchronous digital signal processor.
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Theses and Dissertations |
| Published: |
2008
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/4672 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |