Design of a low-power asynchronous multiplier
This thesis pertains to design and analysis of a 16-bit low-voltage (1.1 V) low-power asynchronous parallel multiplier targeted for a low-power asynchronous digital signal processor.
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| 格式: | Theses and Dissertations |
| 出版: |
2008
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| 在線閱讀: | http://hdl.handle.net/10356/4672 |
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| 機構: | Nanyang Technological University |