High-speed and low-power serial accumulator for serial/parallel multiplier

• Main Authors: Meher, Manas Ranjan, Jong, Ching Chuen, Chang, Chip Hong
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: https://hdl.handle.net/10356/90594; http://hdl.handle.net/10220/6353
• 機構: Nanyang Technological University

This paper presents a new approach to serial/parallel multiplier design by using parallel 1's counters to accumulate the binary partial product bits. The 1's in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) cou...