An area and energy efficient inner-product processor for serial-link bus architecture

A unique word-serial inner-product processor architecture is proposed to capitalize on the high-speed serial-link bus. To eliminate the input buffers and deserializers, partial products are generated immediately from the serial input data and accumulated by an array of small binary counters operatin...

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Bibliographic Details
Main Authors: Meher, Manas Ranjan, Jong, Ching Chuen, Chang, Chip Hong
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2013
Subjects:
Online Access:https://hdl.handle.net/10356/95905
http://hdl.handle.net/10220/11317
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Institution: Nanyang Technological University
Language: English