FPGA implementation of product accumulate codes
129 p.
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2011
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sg-ntu-dr.10356-470302023-07-04T16:11:39Z FPGA implementation of product accumulate codes Koh, Tiong Aik Guan Yong Liang School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering 129 p. Product accumulate (PA) codes are a class of low density parity check (LDPC)-like codes with a well defined structure, which allows flexible rate and length adaptation while maintaining good bit error rate (BER) performance. Compared to turbo codes, they provide similar performance but with significantly less decoding complexity and with a lower error floor. This thesis presents our study on the various design tradeoffs needed for the field programmable gate array (FPGA) implementation of PA codes and on the actual FPGA implementation of the PA type I encoder and decoder (codec). MASTER OF ENGINEERING (EEE) 2011-12-27T05:56:06Z 2011-12-27T05:56:06Z 2009 2009 Thesis Koh, T. A. (2009). FPGA implementation of product accumulate codes. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/47030 10.32657/10356/47030 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering Koh, Tiong Aik FPGA implementation of product accumulate codes |
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129 p. |
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Guan Yong Liang |
author_facet |
Guan Yong Liang Koh, Tiong Aik |
format |
Theses and Dissertations |
author |
Koh, Tiong Aik |
author_sort |
Koh, Tiong Aik |
title |
FPGA implementation of product accumulate codes |
title_short |
FPGA implementation of product accumulate codes |
title_full |
FPGA implementation of product accumulate codes |
title_fullStr |
FPGA implementation of product accumulate codes |
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FPGA implementation of product accumulate codes |
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fpga implementation of product accumulate codes |
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2011 |
url |
https://hdl.handle.net/10356/47030 |
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1772826942736695296 |