Customizable instruction cache hierarchy for embedded systems

146 p.

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Bibliographic Details
Main Author:	Kugan Vivekanandarajah
Other Authors:	Thambipillai Srikanthan
Format:	Theses and Dissertations
Published:	2011
Subjects:	DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures
Online Access:	https://hdl.handle.net/10356/47483
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-47483
record_format	dspace
spelling	sg-ntu-dr.10356-474832023-03-04T00:41:15Z Customizable instruction cache hierarchy for embedded systems Kugan Vivekanandarajah Thambipillai Srikanthan School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures 146 p. Cache hierarchy bridges the ever increasing performance gap between the fast processing core and slow main memory. In an effort to improve the total system performance, the high performance microprocessor designers commit more and more transistor budget for cache memory systems. As a result, power consumption of cache memory subsystems has been increasing notably over each processor generation. Although a number of cache optimization techniques to reduce power consumption have been reported in the literature, power consumption in cache memories is a major concern and accounts for as much as 50% of the total processor power. Since the instruction cache consumes the majority of this power, predictor based schemes have been proposed for the instruction cache hierarchy in an attempt to provide for an overall reduction in the energy delay product. DOCTOR OF PHILOSOPHY (SCE) 2011-12-27T08:25:54Z 2011-12-27T08:25:54Z 2005 2005 Thesis Kugan, V. (2005). Customizable instruction cache hierarchy for embedded systems. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/47483 10.32657/10356/47483 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures
spellingShingle	DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures Kugan Vivekanandarajah Customizable instruction cache hierarchy for embedded systems
description	146 p.
author2	Thambipillai Srikanthan
author_facet	Thambipillai Srikanthan Kugan Vivekanandarajah
format	Theses and Dissertations
author	Kugan Vivekanandarajah
author_sort	Kugan Vivekanandarajah
title	Customizable instruction cache hierarchy for embedded systems
title_short	Customizable instruction cache hierarchy for embedded systems
title_full	Customizable instruction cache hierarchy for embedded systems
title_fullStr	Customizable instruction cache hierarchy for embedded systems
title_full_unstemmed	Customizable instruction cache hierarchy for embedded systems
title_sort	customizable instruction cache hierarchy for embedded systems
publishDate	2011
url	https://hdl.handle.net/10356/47483
_version_	1759856406779920384

Customizable instruction cache hierarchy for embedded systems

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