Implementation of floating point adder and multiplier based on residue number system

• Main Author: Lim, Hue Hsean.
• Other Authors: Chang Chip Hong
• Format: Final Year Project
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/49592
• Institution: Nanyang Technological University

Floating point processor is part of computer system specially designed to execute floating point operations. Typical arithmetic operations are addition, subtraction, multiplication and division. Today, it can be seen that most of the floating point processors are implemented using the weighted number system representation such as binary or decimal. However, their overall operating speed is limited by the carry propagation delay involved in arithmetic operations. Hence, Residue Number System (RNS), which is a non-weighted number system, become very popular and gains the attention in the implementation of fast arithmetic and fault-tolerant computing applications. Its attractive inherent properties such as modularity, parallelism and carries free computation, have speed up the arithmetic computations. Thus, in this project, floating point multiplier and adder based on RNS are proposed and implemented. This report discusses the advantages of residue arithmetic, the binary floating point adder and multiplier architecture and its data path, the implementation of the proposed RNS floating point adder and multiplier, the comparison of the binary and RNS implementation in terms of timing constraint, power and area and finally the limitations involved in RNS implementation.