A full-custom IC design flow high speed design using 16-bit full adder

• Main Author: Teo, Kok Xuan.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/49965
• Institution: Nanyang Technological University

As technology advances, consumers expect faster, smaller and lower power consumption performance. Therefore, it is important and beneficial for an engineer to learn about full-custom IC Electronic Design Automation (EDA) design flow. Many designers try to reduce transistor count in attempt to improve performance such as speed and power consumption. While this may be true, this report very much like a teaching tool aims to illustrate that circuit performances can be improve even with the same topology and transistors count. Cadence IC design flow is discussed and implement to design a high speed 16bit adder. 2 adder designs with same topology transistors count were used and compared. Improvements were further made to the layout of the better design to illustrate improvement without changing transistors count and topology.