Development of a rapid prototyping of FPGA-based digital multiplier

• المؤلف الرئيسي: Toh, Tong San.
• مؤلفون آخرون: Gwee Bah Hwee
• التنسيق: Final Year Project
• اللغة: English
• منشور في: 2012
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/50174
• المؤسسة: Nanyang Technological University

This report is devoted for the implemented of different kinds of multipliers on reconfigurable hardware FPGA using VHDL. The main focuses are on the speed, area of the multiplier and performance comparison. Hardware Multiplication is a basic function often required for system applications such as DSP and process control. Optimizing the speed and area of the multiplier is a major design issue and are usually conflicting constraints because improving speed results mostly in larger areas. This project aimed to determine the best solution by evaluating few multipliers using FPGA for rapid prototyping. This is important because the fabrication of chips and high performance system require components which are as small as possible and less power consumption.