Development of a rapid prototyping of FPGA-based digital multiplier
This report is devoted for the implemented of different kinds of multipliers on reconfigurable hardware FPGA using VHDL. The main focuses are on the speed, area of the multiplier and performance comparison. Hardware Multiplication is a basic function often required for system applications such as DS...
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2012
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| 在線閱讀: | http://hdl.handle.net/10356/50174 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | This report is devoted for the implemented of different kinds of multipliers on reconfigurable hardware FPGA using VHDL. The main focuses are on the speed, area of the multiplier and performance comparison. Hardware Multiplication is a basic function often required for system applications such as DSP and process control. Optimizing the speed and area of the multiplier is a major design issue and are usually conflicting constraints because improving speed results mostly in larger areas. This project aimed to determine the best solution by evaluating few multipliers using FPGA for rapid prototyping. This is important because the fabrication of chips and high performance system require components which are as small as possible and less power consumption. |
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