Design of the low-voltage CMOS analog multiplier

• Main Author: Guo, Lizao.
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/50254
• Institution: Nanyang Technological University

Analog multipliers have wide range of applications in analog signal processing. Multiplying two real-time analog signals is an important operation in filter, mixer and modulator designs. With the shrinking size of transistor and the increasing demand for low-power devices, it is required to design analog multipliers compatible with low supply voltage. The CMOS analog multiplier has been proposed in many configurations but low-voltage low-power CMOS analog multiplier is still a challenging subject in Integrated Circuit design today. In this thesis, a four quadrant CMOS analog multiplier with 1V supply voltage is presented utilizing the 0.18um process technology. The multiplier is capable of accepting 200mV peak-to-peak input voltage at both input ports and has good linearity within this input range.