A comparative energy efficiency analysis on SRAM cell designs
Technology advancement has brought about the continuous scaling of transistors sizes.The decreasing size of transistors led to lower supply voltage being used and hence ultra low power applications. Energy consumption is a factor to consider when it comes to low power applications as one does not wa...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2012
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| Online Access: | http://hdl.handle.net/10356/50281 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Technology advancement has brought about the continuous scaling of transistors sizes.The decreasing size of transistors led to lower supply voltage being used and hence ultra low power applications. Energy consumption is a factor to consider when it comes to low power applications as one does not want too much power to be consumed to lengthen battery life for example, when it comes to mobile applications. This project presents a comparative analysis of 8T and 10T SRAM cells on the active read energy consumption per cycle by implementing a few of the current circuit optimization techniques such as upsizing transistors, partitioning the bitline to local bitlines, boosting the voltage of the read wordline and implementing reverse short channel effect. Based on the simulation results, it can be seen that a good choice of transistor sizes and other careful selection of options for enhancing the performance of the 8T SRAM cells improve the read energy consumption by 47%. When compared to the conventional 10T SRAM cells, it yields an improvement of 35% at 0.4V Vdd and even at the worst case, a reduction of 22% in terms of energy saving at 1.2V Vdd. |
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