Analysis and reduction of mismatch in low power sub-threshold silicon neurons

In this thesis, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron’s current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allow...

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Main Author: Sun, Shuo
Other Authors: School of Electrical and Electronic Engineering
Format: Theses and Dissertations
Language:English
Published: 2013
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Online Access:https://hdl.handle.net/10356/51101
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-511012023-07-04T17:09:35Z Analysis and reduction of mismatch in low power sub-threshold silicon neurons Sun, Shuo School of Electrical and Electronic Engineering VIRTUS IC Design Centre of Excellence Arindam Basu DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this thesis, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron’s current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in ‘calibration’ time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion. We have fabricated a chip containing three different type neuron arrays, synaptic circuits, and input/output AER interfacing circuits. It occupies 2.5mmx5.5mm area using VIS 0.35um technology. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. MASTER OF ENGINEERING (EEE) 2013-01-14T03:26:29Z 2013-01-14T03:26:29Z 2012 2012 Thesis Sun, S. (2012). Analysis and reduction of mismatch in low power sub-threshold silicon neurons. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/51101 10.32657/10356/51101 en 93 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Sun, Shuo
Analysis and reduction of mismatch in low power sub-threshold silicon neurons
description In this thesis, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron’s current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in ‘calibration’ time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion. We have fabricated a chip containing three different type neuron arrays, synaptic circuits, and input/output AER interfacing circuits. It occupies 2.5mmx5.5mm area using VIS 0.35um technology. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Sun, Shuo
format Theses and Dissertations
author Sun, Shuo
author_sort Sun, Shuo
title Analysis and reduction of mismatch in low power sub-threshold silicon neurons
title_short Analysis and reduction of mismatch in low power sub-threshold silicon neurons
title_full Analysis and reduction of mismatch in low power sub-threshold silicon neurons
title_fullStr Analysis and reduction of mismatch in low power sub-threshold silicon neurons
title_full_unstemmed Analysis and reduction of mismatch in low power sub-threshold silicon neurons
title_sort analysis and reduction of mismatch in low power sub-threshold silicon neurons
publishDate 2013
url https://hdl.handle.net/10356/51101
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