Next generation RF CMOS power amplifiers for system-on-chip applications

• Main Author: Pan, Renjing
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits; DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits; DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio; DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems
• Online Access: http://hdl.handle.net/10356/51172
• Institution: Nanyang Technological University

In this dissertation we evaluate the radio frequency (RF) power amplifier implemented in CMOS process. The evaluation is done both theoretically and practically. The theoretical study of the power amplifier consists of its classifications, configurations and issues to be considered during practical design. Two fully-integrated CMOS power amplifiers are designed for a 3.5 GHz mobile WiMAX (IEEE 802.16e standard) subscriber station application to fulfill the research topic of the next generation RF CMOS power amplifiers for System-on-Chip (SoC) applications. The research work is also extended to millimeter wave power amplifiers design for 60 GHz ISM band application. Two power amplifiers are designed using SiGe BiCMOS process for a 60 GHz low power transmitter. The first WiMAX power amplifier is designed to operate at a supply voltage of 1.8 V. By utilizing multiple-stage configuration with LRC feedback loop in the output stage, the comprehensive pre-layout and post-layout simulation results at a supply voltage of 1.8 V indicate a capability to deliver a maximum output power of 24 dBm to a 50 Ω antenna, with an output 1-dB compression point, PO1dB, of 22.35 dBm corresponding to an input power, PI1dB, of -3.01 dBm. A power gain of 25.92 dB and a voltage gain of 26.67 dB can be obtained through a three-stage cascade configuration, and the Power-Added-Efficiency, PAE, at PO1dB is almost 24%. The post-layout and corner simulations are also performed and some discussions on the performance degradation under Process-Voltage-Temperature (PVT) variations are presented. Although this design might not fully fulfill the 3.5 GHz mobile WiMAX requirement, it shows the potential to implement a WiMAX power amplifier in CMOS process under low supply voltage. In order to achieve high saturated power as well as high linearity, the second design uses a four-stage power combination technique to boost the output power. As a result, a 32 dBm of saturated power, PSAT, can be achieved with an input power of -2.733 dBm. A PAE of 48.24% and 15.2% can be obtained at PSAT and at 25 dBm output power, respectively, with a power gain of 35.8 dB from a 3.3 V supply voltage. The schematic simulation results show that this design can fulfill the mobile WiMAX requirement. Both designs are based on Globalfoundries’ 0.18μm IC process. As for the research work into millimeter wave power amplifier design, two power amplifiers are proposed: two-stage and three-stage power amplifiers. The two designs adopt multiple-stage single-ended topology and common-emitter structure for most of the driving stages.