Low-power and robust SRAM design

This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bi...

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Bibliographic Details
Main Author:	Chen, Junchao.
Other Authors:	Gwee Bah Hwee
Format:	Theses and Dissertations
Language:	English
Published:	2013
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:	http://hdl.handle.net/10356/51690
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-51690
record_format	dspace
spelling	sg-ntu-dr.10356-516902023-07-04T16:08:10Z Low-power and robust SRAM design Chen, Junchao. Gwee Bah Hwee School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bitlines. Robustness is enhanced by using asynchronous Quasi-Delay-Insensitive (QDI) technique to reduce the possible synchronous failure in conventional synchronous counterpart, by using novel memory cells to reduce the read and write stability problem in conventional SRAMs as well as by using efficient bit-interleaved structure to increase the soft-error immunity when combined with error correction code (ECC). Master of Engineering 2013-04-08T07:46:34Z 2013-04-08T07:46:34Z 2013 2013 Thesis http://hdl.handle.net/10356/51690 en 77 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Chen, Junchao. Low-power and robust SRAM design
description	This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bitlines. Robustness is enhanced by using asynchronous Quasi-Delay-Insensitive (QDI) technique to reduce the possible synchronous failure in conventional synchronous counterpart, by using novel memory cells to reduce the read and write stability problem in conventional SRAMs as well as by using efficient bit-interleaved structure to increase the soft-error immunity when combined with error correction code (ECC).
author2	Gwee Bah Hwee
author_facet	Gwee Bah Hwee Chen, Junchao.
format	Theses and Dissertations
author	Chen, Junchao.
author_sort	Chen, Junchao.
title	Low-power and robust SRAM design
title_short	Low-power and robust SRAM design
title_full	Low-power and robust SRAM design
title_fullStr	Low-power and robust SRAM design
title_full_unstemmed	Low-power and robust SRAM design
title_sort	low-power and robust sram design
publishDate	2013
url	http://hdl.handle.net/10356/51690
_version_	1772827565174554624

Low-power and robust SRAM design

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