Analysis and design of on-chip antenna and its switch in 65nm CMOS

• Main Author: Deng, Tianwei
• Other Authors: Zhang Yue Ping
• Format: Theses and Dissertations
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits; DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio
• Online Access: http://hdl.handle.net/10356/52078
• Institution: Nanyang Technological University

This thesis can be divided into four parts. In the first part of the work, the simplified model of the chip is presented. The multiple silicon-oxide layers and passivation layers are simplified. The simplified chip model can be simulated in common PC by the 3D EM simulator Ansys HFSS. Besides, the limitations by design rules of standard CMOS process are analyzed for on-chip dipole design work. After building up the simplified model, the on-chip dipole can be designed. In the second part of the work, the model of the on-chip dipole is studied. The formula of the radiation resistance is presented and amended with several key parameters. Then, the formulas of conductor resistance and surface wave resistance are presented. Next, the effect of silicon substrate and silicon-oxide layers is analyzed by employing the on-chip transmission line. The telegraph equation model of the on-chip transmission line is extracted by simulated S parameters. The multiple grids circuit is proposed for the model used in Agilent ADS, SPICE and so on. The mutual coupling between on-chip antenna and spiral inductor or coplanar waveguide is studied, tested and analyzed in the third part. Coupling mechanism is studied based on frequency and spacing between each other and equivalent circuits are presented. Also, coupling effects on on-chip antenna and spiral inductor or coplanar waveguide is discussed. Finally, a switchable balun is design for integration T/R switch with on-chip dipole. Transistor in CMOS is modeled in EM simulator HFSS and T/R switch with on-chip dipole is designed and optimized.