VLSI design & implementation for system-on-chip applications

• Main Author: Sreya Banerjee.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/53417
• Institution: Nanyang Technological University

System-on-a-Chip Integrated Circuits are becoming increasingly popular in today’s world. The Memory Management Unit of these System-on-Chip circuits manage the virtual to physical address translation process. The main component within the Memory Management Unit managing this translation is called the Translation Lookaside Buffer which stores the recently used physical address translations. The requirement of the Translation Lookaside Buffer is to provide fast address translations. The behavior of the Translation Lookaside Buffer is characterized by hit & miss – when the address translation information is present and absent. In the Final Year Project, two types of Translation Lookaside Buffers have been successfully designed – one following the Synchronous design principles and the other Asynchronous. The replacement policy of the Translation Lookaside Buffer is also important in determining its efficiency. In this project, the Least Recently Used replacement policy has been implemented in the design of the Translation Lookaside Buffer. The synchronous and asynchronous design schematics and simulation results have been shown.