CMOS differential logic with signal-independent power consumption

• Main Author: Chen, Wanjing.
• Other Authors: Lau Kim Teen
• Format: Final Year Project
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/54228
• Institution: Nanyang Technological University

Power consumption is always the key problem for the digital circuit design. Also, information leaked by hardware implementation is always the problem for the encryption. Many functional logics have been proposed to solve the problems, including Sense Amplifier Based Logic (SABL), Delay-Based Dual-Rail Precharge Logic (DDPL) and Three-phase Dual-Rail Precharge Logic (TDPL). However, the power consumption of these logic gates was less concerned by the designers. This paper focused on the power consumption of different logic gates. By simulating the dynamic logic circuit and dynamic differential circuit in Cadence, the values of power consumption of those circuits were got and compared. By changing the voltage value of the power supply, a conclusion could be made that reducing the voltage of power supply would reduce the power consumption of the circuits. However, this would also result in longer delay time. Hence, a compromise should be made considering the different function of the logics. For those three functional logic circuits, the power consumption values of them were also got and compared to get a better logic with better performance. It was hard to judge which one was better. One should choose the logic depending on the specific needs.