Low power clock-gated CMOS circuits
With the development of IC design, power consumption of the circuit is always being an important aspect in the digital CMOS circuits. In this project, the main point of the clock-gated CMOS circuit is the low power consumption. What’s more, analysis about the speed, power dissipation and size of tra...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2013
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| Online Access: | http://hdl.handle.net/10356/54372 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | With the development of IC design, power consumption of the circuit is always being an important aspect in the digital CMOS circuits. In this project, the main point of the clock-gated CMOS circuit is the low power consumption. What’s more, analysis about the speed, power dissipation and size of transistors are also concerned. Some more metrics such as power-delay product were also recorded to estimate the performance of the circuits. According to the result of the simulation by Cadence, power consumption mainly depended on the supply voltage. Reducing supply voltage will lead to a longer delay and scaling transistors also had a little effect on the speed. So the speed could be a little bit sacrificed for the less power dissipation when the circuits were applied in portable devices. Some simulations of the circuits were also done in the later part of the project. |
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