VLSI circuit attributes optimization using genetic algorithm

• Main Author: Deshpande, Varun
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/54516
• Institution: Nanyang Technological University

Abstract This report presents the formulation and testing of a suitable Genetic Algorithm to optimize VLSI circuit attributes; Speed (Delay), Power Dissipation and Area. Major focus is on the optimization of Speed and Power dissipation. The vital contributions of the Project are: 1) Understanding the nature of the Genetic Algorithm and how it can be used as an Optimization tool in the field of VLSI Circuits, 2) Generating and coding a suitable GA and tailor it according to wanted parameters, 3) carrying out execution of GA to obtain Optimization results and 4) Analysing results and measurement of success. The combinational circuits which are to be used in testing and optimization are the ISCAS-85 benchmark circuits. The ISCAS-85 gate level Netlist consists of several library cells. The following library cells (verilog HDL files), are used as part of experimentation: Syn_c499, Syn_c880 and Syn_1908. As the Genetic Algorithm is a powerful optimization tool, its application in this project is significant. The algorithm code has been developed using the Perl programming language and is executed using a Perl interpreter on a Windows Operating System, after suitable configuration. The results obtained show that the Genetic Algorithm is indeed a successful and powerful tool to solve optimization problems with respect to Asynchronous Circuits. However, there is balance which needs to be sought in terms of delay (speed) and power dissipation. It depends on the designer as to which aspect of these two are more suitable for application.