Efficient architectures for computation of binary logarithm

• 主要作者: Low, Joshua Yung Lih
• 其他作者: Jong Ching Chuen
• 格式: Theses and Dissertations
• 語言: English
• 出版: 2014
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: https://hdl.handle.net/10356/59971
• 機構: Nanyang Technological University

Logarithmic Number System (LNS) is often used in digital signal processing to simplify complex arithmetic operations. LNS requires data to be converted into the logarithmic domain, i.e., logarithmic conversion. The thesis studies the VLSI architectures for logarithmic conversion. The existing Mitche...