16-bit high speed multiplier design
Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissi...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project |
| Language: | English |
| Published: |
2014
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/60817 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissipation of the multiplier, Wallace Tree Algorithm and Modified Booth Algorithm has been proposed to perform the partial product additions. Also Ripple Carry Adder and Carry Lookahead Adder have been proposed for the final addition of the partial products for any improvement. |
|---|