16-bit high speed multiplier design

Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissi...

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Bibliographic Details
Main Author:	Yeo, Melvin Shung Shii
Other Authors:	Gwee Bah Hwee
Format:	Final Year Project
Language:	English
Published:	2014
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	http://hdl.handle.net/10356/60817
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-60817
record_format	dspace
spelling	sg-ntu-dr.10356-608172023-07-07T17:11:34Z 16-bit high speed multiplier design Yeo, Melvin Shung Shii Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissipation of the multiplier, Wallace Tree Algorithm and Modified Booth Algorithm has been proposed to perform the partial product additions. Also Ripple Carry Adder and Carry Lookahead Adder have been proposed for the final addition of the partial products for any improvement. Bachelor of Engineering 2014-05-30T08:22:34Z 2014-05-30T08:22:34Z 2014 2014 Final Year Project (FYP) http://hdl.handle.net/10356/60817 en Nanyang Technological University 144 Pages application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Yeo, Melvin Shung Shii 16-bit high speed multiplier design
description	Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissipation of the multiplier, Wallace Tree Algorithm and Modified Booth Algorithm has been proposed to perform the partial product additions. Also Ripple Carry Adder and Carry Lookahead Adder have been proposed for the final addition of the partial products for any improvement.
author2	Gwee Bah Hwee
author_facet	Gwee Bah Hwee Yeo, Melvin Shung Shii
format	Final Year Project
author	Yeo, Melvin Shung Shii
author_sort	Yeo, Melvin Shung Shii
title	16-bit high speed multiplier design
title_short	16-bit high speed multiplier design
title_full	16-bit high speed multiplier design
title_fullStr	16-bit high speed multiplier design
title_full_unstemmed	16-bit high speed multiplier design
title_sort	16-bit high speed multiplier design
publishDate	2014
url	http://hdl.handle.net/10356/60817
_version_	1772828145010868224

16-bit high speed multiplier design

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