A low-offset low-quiescent nanometer CMOS power amplifier for portable applications
With the increasing demand for the portable devices, the performance of each component in the portable devices becomes more and more critical. Since headphone amplifier is one of the most important components of the portable headphone, a lot of works have been done on the design of the headphone amp...
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sg-ntu-dr.10356-610612023-07-07T17:10:00Z A low-offset low-quiescent nanometer CMOS power amplifier for portable applications Xiao, Fei Chan Pak Kwong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering With the increasing demand for the portable devices, the performance of each component in the portable devices becomes more and more critical. Since headphone amplifier is one of the most important components of the portable headphone, a lot of works have been done on the design of the headphone amplifier. Quiescent power and distortion are the most significant parameters which describe the performance of the headphone amplifier. Due to its high efficiency and low quiescent power performance, class G amplifier is one of the most common headphone amplifiers. However, the linearity and the overall distortion of the class G amplifier will not be quite good due to its switching structure. Compared to the class G amplifier, a class AB amplifier can be much easier to achieve a good performance on the linearity and overall distortion. In addition, the quiescent power can also be very small by applying some low voltage techniques. In this report, a class AB amplifier with dual supplies ±0.85V and ±0.65V was designed to lower the quiescent power. The performance of low distortion, low quiescent power and good linearity are based on a new push pull stage. The push pull technique can guarantee a stable and linear output and keep the quiescent power at a low level. Another low offset technique called offset current compensation stage is applied in this circuit in order to reduce the input offset voltage of the power amplifier. The simulation results of the overall circuit have shown that the open-loop gain is about 78dB and phase margin is about 48º. The total harmonic distortion of the circuit can attain 98dB, whilst the input offset voltage is as low as 801µV at the quiescent power of only 0.3mW. Bachelor of Engineering 2014-06-04T06:02:38Z 2014-06-04T06:02:38Z 2014 2014 Final Year Project (FYP) http://hdl.handle.net/10356/61061 en Nanyang Technological University 2 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering Xiao, Fei A low-offset low-quiescent nanometer CMOS power amplifier for portable applications |
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With the increasing demand for the portable devices, the performance of each component in the portable devices becomes more and more critical. Since headphone amplifier is one of the most important components of the portable headphone, a lot of works have been done on the design of the headphone amplifier. Quiescent power and distortion are the most significant parameters which describe the performance of the headphone amplifier. Due to its high efficiency and low quiescent power performance, class G amplifier is one of the most common headphone amplifiers. However, the linearity and the overall distortion of the class G amplifier will not be quite good due to its switching structure.
Compared to the class G amplifier, a class AB amplifier can be much easier to achieve a good performance on the linearity and overall distortion. In addition, the quiescent power can also be very small by applying some low voltage techniques. In this report, a class AB amplifier with dual supplies ±0.85V and ±0.65V was designed to lower the quiescent power. The performance of low distortion, low quiescent power and good linearity are based on a new push pull stage. The push pull technique can guarantee a stable and linear output and keep the quiescent power at a low level. Another low offset technique called offset current compensation stage is applied in this circuit in order to reduce the input offset voltage of the power amplifier. The simulation results of the overall circuit have shown that the open-loop gain is about 78dB and phase margin is about 48º. The total harmonic distortion of the circuit can attain 98dB, whilst the input offset voltage is as low as 801µV at the quiescent power of only 0.3mW. |
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Chan Pak Kwong |
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Chan Pak Kwong Xiao, Fei |
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Final Year Project |
author |
Xiao, Fei |
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Xiao, Fei |
title |
A low-offset low-quiescent nanometer CMOS power amplifier for portable applications |
title_short |
A low-offset low-quiescent nanometer CMOS power amplifier for portable applications |
title_full |
A low-offset low-quiescent nanometer CMOS power amplifier for portable applications |
title_fullStr |
A low-offset low-quiescent nanometer CMOS power amplifier for portable applications |
title_full_unstemmed |
A low-offset low-quiescent nanometer CMOS power amplifier for portable applications |
title_sort |
low-offset low-quiescent nanometer cmos power amplifier for portable applications |
publishDate |
2014 |
url |
http://hdl.handle.net/10356/61061 |
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1772825778037194752 |