Low power dual mode CMOS logic
The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2014
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/61339 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance,however, it is accompanied with increased power dissipation. This is achieved with a simple and intuitive design concept.I use the software “Cadence” to compare performance, power dissipation, and speed of the presented DML gates to their CMOS and domino.The DML gates,CMOS and domino what have been mentioned above are all consisted of the NAND gate in this paper. |
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