Low power dual mode CMOS logic

• Main Author: Lei, Yuze
• Other Authors: Lau Kim Teen
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/61339
• Institution: Nanyang Technological University

The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of...