Design of low-voltage differential signaling (LVDS) system
This Report presents a Low Voltage Differential Signaling (LVDS) standard circuit driver and receiver. Circuit Driver is designed under supply voltage of 1.8V. Circuit Driver is implemented using 180nm CMOS technology. Driver circuit uses nominal current of 3.5mA, produced a voltage swing of 350...
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| 主要作者: | |
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2014
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/61434 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | This Report presents a Low Voltage Differential Signaling (LVDS) standard circuit driver and receiver.
Circuit Driver is designed under supply voltage of 1.8V. Circuit Driver is implemented using 180nm CMOS technology. Driver circuit uses nominal current of 3.5mA, produced a voltage swing of 350mV across terminating resistor of 100Ω. Common mode voltage is set to be in 1.2V. CMFB loop is implemented to the circuit to stabilize the common mode input. Proposed driver circuit can achieve theoretical data speed of 1.02 Gbps, while also maintaining low power consumption of 22 mW. Circuit Receiver is designed under similar supply voltage of 1.8V with similar technology of 180 nm CMOS, and able to amplify low swing back to full swing signal. Circuit receiver is expected to retrieve signal with common mode voltage from 650 mV up to 1.5 V, and input differential voltage range from 100 mV to 600 mV.
Process, Voltage, and Temperature variation tests are conducted to ensure proposed circuits to work properly in the range of 1.7 – 1.9 V supply voltage at the temperature range of -40°C to 85°C. |
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