Poly-si nanowire based thin film transistors

• Main Author: Le, Tien Thanh
• Other Authors: Yu Hongyu
• Format: Final Year Project
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics
• Online Access: http://hdl.handle.net/10356/61996
• Institution: Nanyang Technological University

This report compiled all the works that had been done by the author during his Final Year Project subject to fulfill the course requirement under School of Electrical and Electronic Engineering (EEE), Nanyang Technological Univeristy. It mainly consists of 1 main project and 2 sub-projects as briefly described below. Main project: Device fabrication and characterization of a polycrystalline silicon (poly- Si) vertical nanowire (VNW) based Thin Film Transistor (TFT). This part of the report demonstrates the fabrication process as well as device characterization of an inverter. With the NMOS to PMOS ratio of 1:1, the inverter exhibits very good performance with high drive current (~100μA/μm), good subthreshold slope (SS ~80-100mV/dec), low drain-induced barrier lowering (DIBL ~20-60mV/V) and high ION/IOFF ratio (~107). Together with good uniformity, this enables the device to be compatible for system on panel driving circuitry fabrication. CMOS compatible VNW devices could also realize 3D integration that will further improve device packing density and at the same time reduce power consumption.