Low-power non-binary SAR ADC with a two-mode comparator

• Main Author: Li, Jianni
• Other Authors: Yvonne Lam Ying Hung
• Format: Theses and Dissertations
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/62146
• Institution: Nanyang Technological University

For implantable medical devices like artificial pacemakers, high power efficiency is demanded because they are supposed to work 5 to 10 years on a battery. ADC is one of the major blocks as the interface between analog signals and digital logic. Hence, low power ADC with low speed and medium resolution is needed for such applications. These requirements make SAR ADC a suitable choice due to its simple structure and serial operation. However, there is still room for future power efficiency improvement. To lower the power consumption, the method of applying a two-mode comparator was proposed, where the first few steps are completed in the comparator’s low accuracy mode, and the last few steps are completed in the high accuracy mode. However, more errors are resulted in the first few steps, when the comparator is working with low accuracy. To resolve this problem, a generalized non-binary algorithm is applied. The capacitance values of the DAC array were adjusted to achieve better static performance. In this project, an SAR ADC applying the generalized non-binary algorithm with a two-mode comparator is proposed. The capacitance values of the DAC array were adjusted to achieve better static performance, and hence the performance of the proposed ADC is improved. A non-binary ADC with the conventional structure is also constructed for performance comparison. Both ADCs were designed and simulated using GF 40nm technology. The simulation results show that with comparable static performance, the non-binary ADC with a two-mode comparator shows better power efficiency.