Automated scripts for testing verilog designs with iVerilog

• Main Author: Ng, Gary Jia Hao
• Other Authors: Suhaib A Fahmy
• Format: Final Year Project
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Computer science and engineering
• Online Access: http://hdl.handle.net/10356/62552
• Institution: Nanyang Technological University

Writing a testbench to test Verilog designs is a tedious process. The user is required to first have a very clear understanding of the design specifications. After which, a test plan can then be devised to document the test bench architecture and scenarios in detail. Undergraduates often lack the re...