Automated scripts for testing verilog designs with iVerilog
Writing a testbench to test Verilog designs is a tedious process. The user is required to first have a very clear understanding of the design specifications. After which, a test plan can then be devised to document the test bench architecture and scenarios in detail. Undergraduates often lack the re...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2015
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| Online Access: | http://hdl.handle.net/10356/62552 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Writing a testbench to test Verilog designs is a tedious process. The user is required to first have a very clear understanding of the design specifications. After which, a test plan can then be devised to document the test bench architecture and scenarios in detail. Undergraduates often lack the required knowledge. Icarus Verilog, better known as iVerilog, is an open source tool primarily used in the simulation and synthesis of Verilog hardware description language for digital electronics design. With the ability to create simulation models, actual behaviour of the designed device can be tested and used to verify the correctness of the source design. In this project, the use of iVerilog as a potential tool for the decoding of Verilog hardware description language was explored. Python scripts were written to check for the coding bugs or errors of the source design through the usage of testbenches. The resulting output was then further used on the GTKWAVE Analyzer to check for the correctness of the verilog design implemented. To ensure the robustness of the scripts written, these scripts were also tested under different test scenarios to ensure that all its intended functionalities could be performed without any issues. |
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