Low power CMOS and adiabatic arithmetic units

In these years, logic circuits intend to develop towards low energy consumption. Therefore, adiabatic logic was brought up to tackle the problem. In this dissertation, adiabatic theory was introduced and adiabatic logic's, including ECRL, CEPAL and CAL were presented and simulated in C...

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Main Author: Meng, Xing
Other Authors: Lau Kim Teen
Format: Theses and Dissertations
Language:English
Published: 2015
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Online Access:http://hdl.handle.net/10356/64772
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-647722023-07-04T15:24:20Z Low power CMOS and adiabatic arithmetic units Meng, Xing Lau Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering In these years, logic circuits intend to develop towards low energy consumption. Therefore, adiabatic logic was brought up to tackle the problem. In this dissertation, adiabatic theory was introduced and adiabatic logic's, including ECRL, CEPAL and CAL were presented and simulated in Cadence. Power Consumption were compared in various periods. Then five 1-bit adders, conventional CMOS, dynamic, CEPAL, ECRL and CAL were simulated. Power consumption in different supply voltages and periods were compared. Then, 8-bit adders using adiabatic logic's were designed and simulated. At last, conclusions were drawn from the simulation results. Master of Science (Electronics) 2015-06-04T02:00:52Z 2015-06-04T02:00:52Z 2014 2014 Thesis http://hdl.handle.net/10356/64772 en 71 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering
spellingShingle DRNTU::Engineering
Meng, Xing
Low power CMOS and adiabatic arithmetic units
description In these years, logic circuits intend to develop towards low energy consumption. Therefore, adiabatic logic was brought up to tackle the problem. In this dissertation, adiabatic theory was introduced and adiabatic logic's, including ECRL, CEPAL and CAL were presented and simulated in Cadence. Power Consumption were compared in various periods. Then five 1-bit adders, conventional CMOS, dynamic, CEPAL, ECRL and CAL were simulated. Power consumption in different supply voltages and periods were compared. Then, 8-bit adders using adiabatic logic's were designed and simulated. At last, conclusions were drawn from the simulation results.
author2 Lau Kim Teen
author_facet Lau Kim Teen
Meng, Xing
format Theses and Dissertations
author Meng, Xing
author_sort Meng, Xing
title Low power CMOS and adiabatic arithmetic units
title_short Low power CMOS and adiabatic arithmetic units
title_full Low power CMOS and adiabatic arithmetic units
title_fullStr Low power CMOS and adiabatic arithmetic units
title_full_unstemmed Low power CMOS and adiabatic arithmetic units
title_sort low power cmos and adiabatic arithmetic units
publishDate 2015
url http://hdl.handle.net/10356/64772
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