Low power performance analysis of CMOS arithmetic units

• Main Author: Moni, Bhaskar
• Other Authors: Kim Teen Lau
• Format: Theses and Dissertations
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/66426
• Institution: Nanyang Technological University

The dissertation takes into study of ultra-low power methodologies by analyzing full adders constructed with different topologies. Full adders are at the heart of multiple larger circuits which includes multipliers, shifters, data compressors for signal encoding, DSP architectures and ALU which in tum is a major component of the CPU. hi this dissertation, eight different topologies have been analyzed to construct a 1-bit full adder and their performance on the basis of average power consumption, delay and power-delay product has been studied over a voltage range of 900mV to 1.2 V supply voltage and a frequency range of 250 MHz to 1 GHz. The circuits remain functional to voltages as low as 600 mV but the powerless and groundless circuits[22] falter under so low an operating voltage. Added to that the specified operating range by TSMC for the 65 nm technology node is 900 mV to 1.2 V. Out of them, two topologies are selected based on the values of performance parameters such as delay, average power consumption and power delay product to create a three stage 8:2 “lossy” compressor and after that their performance characteristics are also studied. The circuits are simulated in Cadence virtuoso software using TSMC’s 65nm process foundry technology and the results show that the transmission gate topology is the best one considering the measured aspects of the circuits but dynamic logic cannot be neglected owing to it being flexible as in it can switched on and off with the help of a control signal favoring its presence in various electronics equipment.