Design of low power fractional-N phase locked loop for FMCW radar application

Design of low power fractional-N phase locked loop for FMCW radar application

High performance digital phase locked loops (DPLLs) have been proposed as alternatives to traditional phase locked loops (PLLs) based on analog charge pump. DPLLs offer several advantages over their analog counterparts. CMOS technology scaling also favors digital circuits over their analog counterpa...

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Main Author: Liu, Supeng
Other Authors: Zheng Jialing
Format: Theses and Dissertations
Language:English
Published: 2016
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/68940
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-689402023-07-04T16:31:52Z Design of low power fractional-N phase locked loop for FMCW radar application Liu, Supeng Zheng Jialing School of Electrical and Electronic Engineering Zheng Yuanjin DRNTU::Engineering::Electrical and electronic engineering High performance digital phase locked loops (DPLLs) have been proposed as alternatives to traditional phase locked loops (PLLs) based on analog charge pump. DPLLs offer several advantages over their analog counterparts. CMOS technology scaling also favors digital circuits over their analog counterparts. Despite offering significant advantages in area, manufacturability and programmability, the performance of DPLL is limited by performance of its key building blocks including time to digital converter (TDC), high resolution digital controlled oscillator (DCO) and high speed counter in counter-assisted DPLL architecture. In addition, frequency prescaler/divider is another indispensable component in high frequency phase locked loop (PLL) implementations and a major source of power consumption. In this report, each of the building blocks of DPLL is studied and both circuit level and architecture level innovations and implementations are proposed for low power DPLL implementation. ELECTRICAL and ELECTRONIC ENGINEERING 2016-08-16T04:27:33Z 2016-08-16T04:27:33Z 2016 Thesis Liu, S. (2016). Design of low power fractional-N phase locked loop for FMCW radar application. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/68940 10.32657/10356/68940 en 148 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Liu, Supeng
Design of low power fractional-N phase locked loop for FMCW radar application
description High performance digital phase locked loops (DPLLs) have been proposed as alternatives to traditional phase locked loops (PLLs) based on analog charge pump. DPLLs offer several advantages over their analog counterparts. CMOS technology scaling also favors digital circuits over their analog counterparts. Despite offering significant advantages in area, manufacturability and programmability, the performance of DPLL is limited by performance of its key building blocks including time to digital converter (TDC), high resolution digital controlled oscillator (DCO) and high speed counter in counter-assisted DPLL architecture. In addition, frequency prescaler/divider is another indispensable component in high frequency phase locked loop (PLL) implementations and a major source of power consumption. In this report, each of the building blocks of DPLL is studied and both circuit level and architecture level innovations and implementations are proposed for low power DPLL implementation.
author2 Zheng Jialing
author_facet Zheng Jialing
Liu, Supeng
format Theses and Dissertations
author Liu, Supeng
author_sort Liu, Supeng
title Design of low power fractional-N phase locked loop for FMCW radar application
title_short Design of low power fractional-N phase locked loop for FMCW radar application
title_full Design of low power fractional-N phase locked loop for FMCW radar application
title_fullStr Design of low power fractional-N phase locked loop for FMCW radar application
title_full_unstemmed Design of low power fractional-N phase locked loop for FMCW radar application
title_sort design of low power fractional-n phase locked loop for fmcw radar application
publishDate 2016
url https://hdl.handle.net/10356/68940
_version_ 1772825178582024192

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