Design of low power fractional-N phase locked loop for FMCW radar application

• Main Author: Liu, Supeng
• Other Authors: Zheng Jialing
• Format: Theses and Dissertations
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/68940
• Institution: Nanyang Technological University

High performance digital phase locked loops (DPLLs) have been proposed as alternatives to traditional phase locked loops (PLLs) based on analog charge pump. DPLLs offer several advantages over their analog counterparts. CMOS technology scaling also favors digital circuits over their analog counterpa...