Design of a CMOS class AB op amp

Power consumption is always the main concern for every manufacturing factory, and power amplifier is one of the most important structures in circuit design. For designers, building compact and portable devices with low power consumption is the basic requirement. Since the operational transconductanc...

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Main Author: Song, Xinze
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: 2017
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Online Access:http://hdl.handle.net/10356/70693
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-706932023-07-07T16:47:43Z Design of a CMOS class AB op amp Song, Xinze Siek Liter School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Power consumption is always the main concern for every manufacturing factory, and power amplifier is one of the most important structures in circuit design. For designers, building compact and portable devices with low power consumption is the basic requirement. Since the operational transconductance amplifiers (OTA) can only drive capacitance load, a power amplifier is then needed to be the output stage to load resistors. A CMOS Class AB operational amplifier is the best option to meet the low power consumption and high-efficiency requirements. As a beginner with very basic knowledge in circuit design, this project not only presents the whole design procedure of a class AB op-amp but also the tips for beginners, such as how to reduce the offset of the whole circuit. The designed circuit use a wide swing constant transconductance biasing structure to drive each transistor in the saturation region. The main part is composed of a folded cascode amplifier and a push-pull class AB output stage. The class AB output stage is also biased using two floating current sources. The designed circuit provides 77dB open loop gain with a phase margin of 108 degrees. The total harmonic distortion is minimized and the quiescent current is less than 10% of the maximum output drive. The PSRR of the designed circuit is up to 118 dB Cadence Custom IC Design Tools (Virtuoso Front to Back Design Environment, version 5.10.41.500.4.67) based on 0.18μm CSM CMOS N-well process is the design tool required to complete the project. Bachelor of Engineering 2017-05-09T06:18:42Z 2017-05-09T06:18:42Z 2017 Final Year Project (FYP) http://hdl.handle.net/10356/70693 en Nanyang Technological University 48 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Song, Xinze
Design of a CMOS class AB op amp
description Power consumption is always the main concern for every manufacturing factory, and power amplifier is one of the most important structures in circuit design. For designers, building compact and portable devices with low power consumption is the basic requirement. Since the operational transconductance amplifiers (OTA) can only drive capacitance load, a power amplifier is then needed to be the output stage to load resistors. A CMOS Class AB operational amplifier is the best option to meet the low power consumption and high-efficiency requirements. As a beginner with very basic knowledge in circuit design, this project not only presents the whole design procedure of a class AB op-amp but also the tips for beginners, such as how to reduce the offset of the whole circuit. The designed circuit use a wide swing constant transconductance biasing structure to drive each transistor in the saturation region. The main part is composed of a folded cascode amplifier and a push-pull class AB output stage. The class AB output stage is also biased using two floating current sources. The designed circuit provides 77dB open loop gain with a phase margin of 108 degrees. The total harmonic distortion is minimized and the quiescent current is less than 10% of the maximum output drive. The PSRR of the designed circuit is up to 118 dB Cadence Custom IC Design Tools (Virtuoso Front to Back Design Environment, version 5.10.41.500.4.67) based on 0.18μm CSM CMOS N-well process is the design tool required to complete the project.
author2 Siek Liter
author_facet Siek Liter
Song, Xinze
format Final Year Project
author Song, Xinze
author_sort Song, Xinze
title Design of a CMOS class AB op amp
title_short Design of a CMOS class AB op amp
title_full Design of a CMOS class AB op amp
title_fullStr Design of a CMOS class AB op amp
title_full_unstemmed Design of a CMOS class AB op amp
title_sort design of a cmos class ab op amp
publishDate 2017
url http://hdl.handle.net/10356/70693
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