Asynchronous QDI library cell layout development and characterization

• Main Author: Hutapea, Samuel Frederick
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/70774
• Institution: Nanyang Technological University

Synchronous circuits have been the prevalent choice of the electronics industry over asynchronous circuits. This is mainly due to the simplicity of data synchronization in synchronous circuits, brought about by usage of global clock signal. However, as more complex circuits are in demand, timing constraint become increasingly problematic for synchronous circuits. As a consequence, more studies on asynchronous circuits are conducted to discover their effective application for industrial needs. Compared to their synchronous counterpart, asynchronous circuits are found to consume less operating power, have no clock skew issues and therefore be capable of operating at higher speed, have better robustness towards process, voltage, and temperature (PVT) variations, among other advantages. In this Final Year Project (FYP), quasi-delay-insensitive (QDI) approach with Pre-Charged Half-Buffer (PCHB) pipeline template is used to implement asynchronous library cells. The library cells consist of 2-input OR/NOR gate, 2-input XOR/XNOR gate, 3-input AO/AOI gate, 3-input OA/OAI gate, and full adder circuit. The main objective of the FYP is to implement their respective layout designs, adhering to Design Rules Check (DRC) and Layout Versus Schematic (LVS) verification checks. In addition, to predict the behavior of the five library cells, pre-layout simulation was conducted on their corresponding schematic designs.